As liquid crystal display (LCD) devices develop towards a low cost, a light weight, a low power consumption and high reliability, LCDs using a plurality of gate drive chips and a plurality of source drive chips have been developed. In such an LCD, scan signals are provided by the plurality of gate drive chips, data signals are provided by a plurality of source drive chips, and signal line patterns are formed on a glass substrate.
The LCD comprises a liquid crystal panel, which is formed by an upper substrate, an intermediate liquid crystal layer and a lower substrate in combination. The liquid crystal panel comprises a plurality of data lines arranged in a column direction and a plurality of scan lines arranged in a row direction. A plurality of thin-film transistors (TFT switches) are disposed in the form of an array at intersections between the plurality of data lines and the plurality of scan lines, and liquid crystal capacitors are formed between the TFTs and a common electrode.
Due to the delay of the data signals and the scan signals caused by resistances of the data lines and the scan lines in the liquid crystal panel, the pulse width of the gate driving signals is reduced and the charging time of the TFT switches is shortened. As the LCD devices are developing towards a high resolution and a high frame rate, the aforesaid problem leads to a shortened average charging time of the TFT switches within a period, thus resulting in degradation of the image frame quality.